1. Field of the Invention
This invention relates to pulse responsive input circuits for integrated circuit devices and particularly to circuits for generating internal timing signals which are intended to have a predetermined timing relationship with respect to externally controlled timing intervals.
2. Prior Art
Integrated circuit devices are subject to a great many parametric variables, both as a result of differing processing parameters and operating environment parameters. These variables cause circuit performance to vary considerably, making design of the circuits difficult, particularly when the designed circuit is intended to share a common interface with one or more additional integrated circuits. Designers have provided many techniques and circuits which are intended to compensate for variable parameters such that the operation of the integrated circuit device can be guaranteed to remain within specified limits, provided the integrated circuit is operated under conditions identified in a product specification.
IGFET integrated circuits are particularly sensitive to a number of different variable parameters which are determined to a large extent on variables present during their manufacture. A number of techniques are known which are intended to compensate for these variable parameters such as threshold voltage, diffusion resistance, physical dimensions and other variables. For example, the article, "FET Device Parameters Compensation Circuit" by H. O. Askin et al, IBM Technical Disclosure Bulletin, Vol. 14, No. 7, December 1971, pp. 2088-2089, teaches a biasing circuit for generating the gate voltage of the load device of an IGFET inverter in which a series of diode-connected IGFETs are used to clamp the load gate voltage to a voltage equal to a predetermined number of threshold voltage drops above ground. This circuit tends to minimize the effect that variable supply voltage and device parameters have on the load device current and power dissipation. F. Grunberg et al in their article, "A Bias Circuit Compensated for Threshold and Supply Variations", IBM Technical Disclosure Bulletin, Vol. 16, No. 1, June 1973, pp. 25-26, teach a similar circuit in which the load gate bias voltage is equal to an on-chip generated reference voltage plus a fixed number of threshold voltage drops. R. H. Kruggel in his article "High-Performance Enhancement Mode FET Logic", IBM Technical Disclosure Bulletin, Vol. 17, No. 8, January 1975, p. 2230, teaches a similar circuit using an external reference voltage to bias a bootstrap driver circuit in which the gate drive voltage (Vg-Vt) of the load device equals the reference voltage.
Another approach to compensating load gate biasing voltage in response to supply voltage variations is taught in U.S. Pat. No. 3,757,200 to Cohen. Here a negative feedback circuit including a pair of inverting amplifiers is used to limit the expected increase in current and power dissipation in the driver circuit in response to changes in supply voltages.
In each of the above references, the primary objective is to stabilize the load gate voltage by providing off-setting compensation when parameter changes tend to raise or lower the load gate bias voltage. In the following references, various techniques are used which tend to over compensate the load gate bias voltage such that the current of the load devices is stabilized.
U.S. Pat. No. 3,508,084 to Warner, Jr. is of interest as it teaches circuits for achieving various biasing effects for IGFET devices, including circuits for providing current and/or voltage regulation. FIGS. 14 and 17 of that patent describe circuits in which a negative resistance effect is achieved in an IGFET connected across a variable source of drain to source voltage. A decreasing load gate bias voltage is provided through the use of a voltage divider including a small, high impedance, pull-up device and a large, low impedance, pull down device having its gate electrode coupled to a chain of diode-coupled devices such that the large device becomes conductive after the supply voltage threshold voltage drops. The proportional increase in current of the large device with respect to the substantially constant current of the small device causes the gate voltage to decrease quickly once the large device begins to conduct.
U.S. Pat. No. 4,008,406 to Kawagoe is of interest as it teaches the use of a negative resistance circuit, similar to FIG. 14 of Warner, Jr., in which the load gate bias voltage for an inverter circuit is provided by a pull up resistor and a supply voltage responsive pull-down device for the purposes of reducing the over-compensation of the load gate bias voltage, in response to changes in the supply voltage, such that the generated bias voltage is more nearly constant.
U.S. Pat. No. 3,970,875 to Leehan is of interest as it teaches a load gate bias compensation circuit in which device parameters and supply voltage variations are compensated for by the use of a circuit in which an increasing proportion of the gate bias signal is applied to the inverting input terminal of a differential amplifier circuit. When the generated gate bias signal is increased above a reference voltage generated by an on-chip voltage divider, a portion of the increase is feedback to generate a new gate bias voltage less than the original increased voltage. Since the reference voltage will increase with increasing supply voltage a net attenuated increase in the gate bias voltage will be experienced by a corresponding increase in supply voltage, such that the gate voltage tends to stabilize at a voltage equal to the reference voltage. Since the reference voltage increases with increasing supply voltage, the gate bias voltage will also increase.
U.S. Pat. No. 4,016,434 to De Filippi is also of interest as it teaches another load gate biasing circuit using an inverting amplifier, similar to that of Leehan. Although De Filippi recognizes that it is desireable to compensate for increasing drain supply voltage by decreasing the magnitude of the load gate bias voltage, insufficient information is provided to determine the intended effect on load device current or load device power dissipation. In addition, the circuit requires that the load devices be driven in their linear mode of operation such that load device current and power dissipation are a function of drain supply voltage. The circuit also requires an additional external power supply for which no compensation is described. Thus, although increases in supply voltages will be compensated for by a decrease in gate bias voltage, no suggestion is made as to the net effect on either load device current or power dissipation.
Although the prior art teaches various techniques to compensate for both device parameter and supply voltage variations, the intended results of such techniques have previously been to provide compensation in such a manner as to essentially stabilize the circuit to be substantially insensitive to various parameter changes so that various characteristics such as circuit performance and power dissipation are limited to minimum ranges.